Method for vertically integrating active circuit planes and vertically integrated circuit produced using said method

ABSTRACT

In a method for vertically integrating active circuit planes, a first substrate having at least one integrated circuit in a first main surface thereof and further having connecting areas for the integrated circuit as well as outer connecting areas on the first main surface is provided in a first step. A second substrate having at least one integrated circuit in a first main surface thereof and further having connecting areas for the integrated circuit as well as open or openable areas on the first main surface is provided. The first main surfaces of the first and second substrates are joined in such a way that the connecting areas of the first substrate are connected to those of the second substrate in an electrically conductive manner in such a way that the outer connecting areas of the first substrate are in alignment with the open or openable areas of the second substrate. Subsequently, the second substrate is thinned and the outer connecting areas are exposed through the open or openable areas. The resultant chips can be further processed making use of standard methods.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for vertically integrating twoactive circuit planes. In addition, the present invention relates tovertically integrated circuits produced by means of such methods.

2. Description of Prior Art

Integrated circuits arranged in a substrate are located essentially inthe vicinity of a main surface of the substrate. In integrated circuitsthe active life of the transistors takes place only in the uppermostplane of the substrate, e.g. of the silicon crystal, in a thicknessrange of less than 2 μm. The residual, a few hundred microns thicksilicon of the substrate is not required for the circuit function.Hence, increasing efforts have been made for some time to utilize thethird dimension, i.e. the thickness dimension more effectively.

The production of an integrated circuit e.g. in CMOS technology normallycomprises far more than 100 individual process steps; each of theseprocess steps must be mastered separately with a yield of approx. 100%so as to obtain a reasonable yield. Attempts to build up further circuitplanes by further processing on existing planes so as to directlyintegrate an additional circuit plane in this way would mean that twicethe number of process steps has to be carried out, whereby the demandson the yield would increase exponentially. Hence, such a utilization ofthe thickness dimension cannot be realized in a sensible way.

The joining of two wafers which have been: processed independently ofone another will, however, only entail a small number of additionalsteps for the individual wafer. More recent solutions are thereforebased on the stacking of fully processed chips, the contacts protrudingon one side and being wired together. Such techniques are disclosed e.g.in M. F. Suer, et al: High Density 3D Packaging”, Proc. VLSI PackagingWorkshop (1991), and C. L. Bertin, et al: “Evaluation of aThree-Dimensional Memory Cube System”, IEEE Transactions on Components,Hybrids and Manufacturing Technology, vol. 16(8), p. 1006, (1993). Thesemethods are, however, only suitable for components having a small numberof terminals, e.g. for storage components, but not for logic unitshaving a large number of terminals.

Other concepts are based on three-dimensional multichip moduletechniques (3D-MCM techniques). In the case of these techniques severalmultichip modules are stacked one on top of the other. This is done insuch a way that one or a plurality of chips are mounted on a support soas to define a multichip module in common, whereupon a plurality ofsupports is joined and wired together. Such techniques are describede.g. in H. Nakanishi, et al: “Development of High Density Memory ICPackage by Stacking IC Chips”, Proc. IEEE Electronic Components andTechnology Conference, p. 634 (1995); C. G. Massit, G. C. Nicolas: “HighPerformance 3D MCM Using Microtechnologies”, Proc. IEEE ElectronicComponents and Technology Conference, p. 641 (1995); J. Barret, et al:“Performance and Reliability of a Three-Dimensional Plastic MouldedVertical Multichip Module (MCM-V)”, Proc. IEEE Electronic Components andTechnology Conference, p. 656 (1995); and they are also described inU.S. Pat. No. 5,202,754.

DE 4433846 A, DE 4433845 A, DE 4433833 A and U.S. Pat. No. 5,563,084additionally describe vertical integration methods which are based on aso-called interchip-via concept (ICV concept). According to thisconcept, wafers are first processed by means of standard processes.Then, two wafers are joined, the upper wafer being thinned to athickness of approx. 10 μm for the purpose of stacking and being thenglued onto the lower wafer. Subsequently, the electric connectionsbetween the upper plane and the lower plane are established by means ofa trench production method which is normally used in the field ofsemiconductor technology, but which has been modified. When the ICVconcept is used, the active side of the respective wafer is arranged onthe top so that the stacking of a plurality of planes is, in principle,possible, but the contacts from one plane to the next must be passedthrough the wafer. For this through connecting processes are necessarywhich require temperatures above 400° C. The ICV concept is additionallydisadvantageous insofar as auxiliary supports are required for thinningthe upper wafer and that complicated rebonding processes have to becarried out consequently.

DE 44 27 515 C1 describes a method for producing a three-dimensionalcircuit arrangement comprising the steps of glueng a substrate disc,which comprises components in a first main surface thereof, onto asupporting plate, thinning it and dicing it by an etching process, afterthe application of a photoresist mask, making use of the photoresistmask as an etching mask, so that splintering of the thinned substratediscs is avoided and so that a better utilization of the material isachieved.

DE 42 38 137 A1 describes a method for producing devices withcomponents, which are produced from,various materials.

DE 195 16 487 C1 discloses a method for vertically integratingmicroelectronic systems in the case of which two substrates areconnected front to front. The term front here describes the side of thesubstrate on which circuit layers and associated metallizations areformed. A first substrate is prepared by forming a viahole therein fromthe front of the substrate; this viahole fully penetrates at least thecircuit layers and it extends through a metallization on the front ofthe first substrate. Subsequently, the front of the first substrate isjoined to the front of a second substrate, the metallization on thefront of the first substrate being in alignment with a metallization onthe front of the second substrate. After the joining, the alignedmetallizations on the first and on the second substrate are notinterconnected in an electrically conductive manner. This electricallyconductive connection is achieved in that the first substrate is thinnedto such an extent that the viahole is open at the back, whereuponinsulating layers on top of the metallization of the second substrateare removed through the viahole so that the metallizations on the firstand second substrates are connected in an electrically conductive mannerby filling the viahole with a conductive material.

SUMMARY OF THE INVENTION

It is the object of the present invention to provide a method forvertically integrating active circuit planes which permits a substantialsimplification of process control.

This object is achieved by a method for vertically integrating activecircuit planes in the case of which a first substrate comprising atleast one integrated circuit in a first main surface thereof and furthercomprising connecting areas for the integrated circuit as well as outerconnecting areas on the first main surface is provided in a first step.In addition, a second substrate comprising at least one integratedcircuit in a first main surface thereof and further comprisingconnecting areas for the integrated circuit as well as open or openableareas on the first main surface thereof is provided. The first mainsurfaces of the first and second substrates are joined in such a waythat the connecting areas of the first substrate are connected to thoseof the second substrate in an electrically conductive manner in such away that the outer connecting areas of the first substrate are inalignment with the open or openable areas of the second substrate.Subsequently, the second substrate is thinned and the outer connectingareas are exposed through the open or openable areas.

The present invention is preferably so conceived that the first and thesecond substrate are a first and a second wafer, each comprising aplurality of integrated circuits arranged in the first main surfacethereof and connecting areas arranged on the first main surface andassociated with the respective integrated circuits. The first mainsurface of the first substrate or first wafer may have provided thereonouter connecting areas which, after the joining of the first and secondsubstrates or first and second wafers, are arranged in such a relationto open areas in the second substrate or second wafer that they areaccessible through the open areas in the second substrate or secondwafer. It follows that, when the second substrate has been thinned back,external contacting of outer connections of the integrated circuitarranged in the first substrate or wafer can be achieved.

When the first and the second substrate are a first and a second wafer,a dicing step is carried out, when the method according to the presentinvention has been executed, so as to divide the multi-layer structureproduced into a plurality of vertically integrated circuits or multichipmodules which are each defined by two interconnected integratedcircuits.

The present invention additionally provides a vertically integratedcircuit comprising a first integrated circuit in a first main surface ofa first substrate, connecting areas for the first integrated circuit onthe first main surface of the first substrate, a second integratedcircuit in a first main surface of a second substrate, and connectingareas for the second integrated circuit on the first main surface of thesecond substrate. The first main surfaces of the first and secondsubstrates are joined in such a way that the connecting areas for thefirst integrated circuit are connected to the connecting areas for thesecond integrated circuit in an electrically conductive manner.

According to the present invention the main surfaces of the first andsecond substrates, in which the integrated circuits are formed, areconnected to one another. Hence, only extremely short connections arerequired from one circuit plane to the next; these extremely shortconnections permit higher system speeds and they help to minimize thedissipation power. According to the present invention, the individualcircuit planes are preferably processed as wafers independently of oneanother, the individual wafers being joined only towards the end of thesequence of production steps. This has the effect that the joining ofthe two wafers, which have been processed independently of one another,necessitates only a small number of additional steps, for the individualwafer. A high yield can therefore be achieved according to the presentinvention. In addition, the individual planes can be produced indifferent technologies, e.g. CMOS bipolar, high-voltage standard CMOS,low-voltage standard CMOS or SOI standard CMOS (SOI=silicon oninsulator). The use of highly complex universal technologies istherefore not necessary.

The utilization of the third dimension in the case of integratedcircuits opens up a great variety of fields of application. Theintegration density can be increased, which means that space can besaved. Concrete fields of application are the hardware realization ofcoding methods, compression methods and data reduction methods in thefield of telecommunications or of real-time image processing methods.The present invention is particularly suitable for portable systems,e.g. mobile phones, or for safety systems making use of the so-calledcryptotechnology. In the case of the latter, individual circuit elementsare distributed over the various planes so that, if the circuit planesare opened later on, the circuit function will no longer beidentifiable. It is therefore clearly evident that the present inventioncan be used advantageously in great number of fields.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following preferred embodiments of the present invention will beexplained in detail making reference to the drawings enclosed in whichidentical elements are designated by identical reference numerals and inwhich:

FIGS. 1a) and 1 b) show schematic cross-sectional views of a first andof a second substrate used in the method according to the presentinvention;

FIGS. 2a) and 2 b) show schematic top views of the first and of thesecond substrate according to FIG. 1a) and 1 b);

FIGS. 3a) to 3 c) show schematic cross-sectional views for illustratingthe production steps of one embodiment of the method according to thepresent invention;

FIG. 4 shows a schematic top view of an alternative embodiment of asubstrate which is to be used for the method according to the presentinvention; and

FIG. 5 shows a schematic top view of a further alternative embodiment ofa substrate which is to be used for the method according to the presentinvention.

DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

According to preferred embodiments of the present invention, two wafersare produced by identical or different standard production methods. InFIGS. 1a) and 1 b) schematic cross-sectional views of two such wafersare shown, the wafer 2 shown in FIG. 1a) being referred to as upperwafer in the following, whereas the wafer 4 shown in FIG. 1b) will bereferred to as lower wafer in the following.

The upper wafer 2 is provided with a plurality of connecting areas 6which will be referred to as inner connecting areas in the following,since they are intended to be used for establishing a direct connectionto inner connecting areas 8 of the lower wafer 4. The respectiveconnecting areas 6 and 8 are arranged above integrated circuits (notshown) formed in the wafers 2 and 4. The integrated circuits are so tospeak located in the upper main surfaces of the two wafers, i.e. forexample in a thickness range of less than 2 μm below the upper mainsurface. The lower wafer 4 is additionally provided with outerconnecting areas 10 which are arranged on the upper surface thereof;these connecting areas can also be seen in the top view of FIG. 2b). Theupper wafer 2, however, is provided with recesses 12 in the area inwhich the lower wafer 4 is provided with the connecting areas 10; in theembodiment shown, these recesses 12; are filled with a polymer.Furthermore, the upper wafer is provided with recesses 14 which areformed in the area of future saw paths 16 for dicing multi-layermodules. In the embodiment shown also the recesses 14 are filled with apolymer. The individual chips 18 are already defined by the recesses 14in this upper wafer 2. Also in the top view of FIG. 2b), the future sawpaths 16 are already schematically shown so that the structure of theindividual chips 18 can also be seen in this figure.

The recesses 12 and 14 are formed e.g. by means of conventional deepetching processes in the upper surface of the upper wafer 2. The depthof the etchings corresponds approximately to the future thickness of theupper wafer 2 when this upper wafer has been subjected to thinning, aswill be explained in detail in the following with respect to FIG. 3b). Apolymer is then preferably introduced into these etchings, as has beenexplained above.

As can especially be seen from the top views of FIG. 2a) and 2 b), theindividual chips 18, which are still present in a connected waferarrangement, are identical in area and they are provided withmirror-inverted matching inner connecting areas 6 and 8 whose positionon the chip surface can be selected freely. These inner connecting areas6 and 8 are used later on for establishing the electric connectionsbetween the two planes defined by the upper and the lower wafer. Theupper and the lower wafer, which are shown in FIG. 1a) and 1 b), arethen joined in accordance with the present invention so as to form amulti-layer structure.

FIG. 3a) shows the two wafers 2 and 4 after they have been joined. Forthis purpose, the wafers 2 and 4 are adjusted relative to one another insuch a way that the respective surfaces thereof, on which the innerconnecting areas 6 and 8 are formed, are arranged in opposedrelationship with one another. As can be seen in FIG. 3a), the innerconnecting areas 6 of the upper wafer 2 are aligned with the innerconnecting areas 8 of the lower wafer 4. At this position the two wafersare connected mechanically and electrically, whereby the innerconnecting areas 6 of the upper wafer 2 will be connected in anelectrically conductive manner to the inner connecting areas 8 of thelower wafer 4.

For connecting the two wafers both mechanically and electrically, alarge number of methods, most of then known from the field of flip-chiptechnology, can be used, e.g. thermocompression bonding, alloying,soldering or joining by means of an adhesive. A preferred form is theuse of an adhesive, since this will produce a full-area connection,whereas in the case of the other methods it will still be necessary tofill the gap with a so-called underfiller. When an adhesive is used, twovariants can be differentiated. On the one hand, a non-conductiveadhesive can be used, the electric contact between the inner connectingareas 6 and 8 being then established by means of a direct contact of theconnecting areas which is maintained by the adhesive matrix.

In the embodiment of the method according to the present invention shownin FIGS. 3a) to 3 c), an anisotropic conductive adhesive 22 has,however, been used, in the case of which the electric contact betweentwo opposed connecting areas 6 and 8 is established via small conductiveballs 20 which are arranged in the adhesive. It will be advantageous totake care that, when joining the wafers by means of an adhesive, thejoint should be as uniform and as thin as possible, which means that thebump height of the connecting areas will be reduced to a large extent.When the two wafers 2 and 4 have been joined by means of an adhesive,the structure shown in FIG. 3a) is obtained.

Taking this structure as a basis, the upper wafer 2 is thinned from itsmain surface, which is located in opposed relationship with the mainsurface having the connecting areas 6 arranged thereon, in the case ofthe embodiment shown. The upper wafer can e.g. be thinned to a residualthickness of≦50 μm. As has already been explained hereinbefore, therecesses 12 and 14 in the upper wafer 2 preferably have a depth whichcorresponds to the thickness of the upper wafer 2 after thinning of thiswafer. In this way, the structure shown in FIG. 3b) is obtained afterthe thinning; in this structure, the polymer-filled recesses or, to beexact, openings 12 and 14 fully extend through the upper wafer 2. Therecesses 12 and 14, which are filled with polymer at this stage of theproceedings, are necessary so that the position of the individual chips18, FIG. 2a) and 2 b), can remain identifiable and so that anaccessibility to the outer connecting areas 10 on the lower wafer 4 canadditionally be realized later on.

The fact that the recesses 12 and 14 are filled facilitates the thinningof the upper wafer 2. It has already been explained that, depending onthe residual thickness of the upper wafer 2 and depending on the waferconnection process used, the recesses in the upper wafer can be filledwith a polymer in such a way that they are flush with the surface;alternatively, the adhesive 22 provided as connection element can alsobe used for filling the recesses.

When the upper wafer 2 has been thinned in this way, the polymer fillingis removed from the recesses 12 and 14 in accordance with the preferredembodiment according to the present invention and also the adhesivearranged below these polymer fillings of recesses 12 and 14 is removed.On the basis of these steps, the structure shown in FIG. 3c) isobtained. As can be seen, the outer connecting areas 10 of the lowerwafer 4 are accessible through the now open recesses 12 in the upperwafer 2. When executing the above-mentioned process of removing thepolymer from the recesses 12 and of eliminating the underlying adhesive,the polymer contained in recesses 14 and the underlying adhesive can beremoved simultaneously so that the openings 24 shown in FIG. 3c) areobtained. Along the resultant openings 24 the dicing step will becarried out later on so as to produce individual chip modules. Thestructural design shown in FIG. 3c) can be subjected to furtherprocessing like a conventional standard wafer, i.e. it can e.g.subjected to dicing by means of suitable diamond saws or the like.Alternatively to the embodiment shown, it is also possible to subjectthe lower wafer 4 to thinning, if the total thickness of the module tobe produced should be very thin. The thinning of the upper and lowerwafers 2 and 4 can be carried out by means of conventional techniques,such as grinding, etching polishing, and the like.

After dicing along the saw paths 16, the chip modules 18 according tothe present invention are obtained, which comprise two integratedcircuits arranged in different substrates. The two substrates areinterconnected in such a way that the surfaces thereof, in which therespective integrated circuits are formed, face each other. Furthermore,very short connection paths can be realized due to the fact that theconnecting areas of the respective integrated circuits are connecteddirectly.

FIG. 4 shows a schematic top view of an alternative embodiment of theabove wafer. Other than in the case of the above-described embodiment,the embodiment shown in FIG. 4 is not provided with individuallyproduced recesses 12 for the outer connecting areas 10 of the lowerwafer, but a broad frame 36 is provided, which comprises saw paths 14and recesses 40 for outer connecting areas 10 along the individual chips18. This arrangement necessitates in any case that the outer connectingareas 10 are arranged on the lower wafer 4 along the edge of theindividual chips. An alternative arrangement of the inner connectingareas 6 and of the recesses 12 for the outer connecting areas on thesecond wafer is shown in FIG. 5. The inner connecting areas 6 and therecesses 12 are in this case arranged substantially alternately withinthe respective chips 18. It is, however, apparent that arbitraryarrangements of inner connecting areas and recesses for the outerconnecting areas on the first wafer are possible as long as amirror-inverted corresponding arrangement of the recesses 12 and of theouter connecting areas 10 is provided on the lower wafer 4.

The present invention provides a large number of advantages. By means ofthe layer structure very high integration densities are achieved, anextremely thin thickness of the overall structure being, however, stillpossible. Due to the extremely short connections between the circuitplanes, it is, additionally, possible to realize circuit modules whichcan be operated at very high frequencies and with a very low drivingpower. In addition, standard processes will largely suffice to executethe methods according to the present invention. The wafer or the waferscan be thinned without using auxiliary supports. Finally, the wafers canbe connected without any high-temperature steps being necessary. Itfollows that the present invention provides an extremely economicalmethod for producing VLSI circuits and, due to a low reject rate and thesimple production method, economy-priced multichip modules.

The chips produced according to the present invention can be furtherprocessed by means of standard methods.

What is claimed is:
 1. A method for vertically integrating activecircuit planes, comprising the following steps: providing a firstsubstrate comprising at least one integrated circuit in a first mainsurface thereof and further comprising connecting areas for theintegrated circuit as well as outer connecting areas on said first mainsurface; providing a second substrate comprising at least one integratedcircuit in a first main surface thereof and further comprisingconnecting areas for the integrated circuit as well as open or openableareas on said first main surface; joining the first main surfaces ofsaid first and second substrates in such a way that the connecting areasof the first substrate are connected to those of the second substrate inan electrically conductive manner, and in such a way that the outerconnecting areas of the first substrate are in alignment with the openor openable areas of the second substrate; thinning the secondsubstrate; and exposing the outer connecting areas through the open oropenable areas.
 2. A method according to claim 1, wherein said first andsecond substrates are joined in such a way that the connecting areas onsaid first and second substrates are in alignment with one another.
 3. Amethod according to claim 1, wherein said second substrate has openareas provided therein so that, when said second substrate has beenthinned, the outer connecting areas are accessible through the secondsubstrate.
 4. A method according to claim 1, wherein the secondsubstrate has provided therein openable areas, said openable areas beingopened after the thinning of the second substrate, so that the outerconnecting areas will be accessible through said second substrate.
 5. Amethod according to claim 1, wherein said first and second substratesare joined by means of an adhesive, the parts of the adhesive coveringthe outer connecting areas being removed through the open areas of thesecond substrate.
 6. A method according to claim 1, wherein said secondsubstrate is thinned from the second main surface thereof, which isopposed to the first main surface, in such away that the open oropenable areas fully penetrate the second substrate.
 7. A methodaccording to claim 1, wherein the first and the second substrate are afirst and a second wafer, each of said wafers having a plurality ofintegrated circuits in the first main surface thereof and respectiveassociated connecting areas on said first main surface.
 8. A methodaccording to claim 7, wherein the second wafer is provided with open oropenable separation grooves defining positions for saw paths for dicingthe respective connected integrated circuits in said first and secondwafers.
 9. A method according to claim 8, wherein said separationgrooves fully penetrate the second wafer after the thinning of saidsecond wafer.
 10. A method for producing multichip modules according toclaim 7, further comprising the step of dicing the multichip structureso as to obtain a plurality of multichip modules.